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Nov. 4, 2009

MIPS Technologies is announcing two new MIPS-32 processor cores, including one that's optimized for Linux. Both the M-14K core and the M-14KC support MIPS' micro instruction set architecture, enabling 1.5 DMIPS/MHz performance and advanced code compression that can reduce code size by 35 percent.

Both the M-14K and M-14KC cores are aimed at cost-sensitive embedded applications, says MIPS Technologies. The new chips are said to be the first MIPS32-compatible cores to offer the new microMIPS instruction set architecture, which is said to maintain 98 percent of MIPS32 performance while reducing code size by 35 percent.

As a result of this compression, the cores enable "significant silicon cost savings," while offering reduced memory access and more efficient use of the instruction cache, thereby helping to reduce system power consumption, claims the company.

Previous MIPS32 cores have included the 24K core and the multi-thread capable 34K core. MIPS also offers a line of MIPS64 cores used in high-end networking processors from Cavium and Tilera, among others.

The base-level M-14K core uses the MIPS32 4K micro-architecture, and is optimized for MCU and real-time embedded applications. It offers reduced interrupt latency and flash acceleration, as well as debug features including iFlowTrace, says MIPS.

The core also supports interconnect interfaces that use AHB Lite, a subset of AHB used in designs that are limited to a single bus master, the company adds.

The new cores' micro architecture offers 32-bit performance with 16-bit code size for most instructions, says MIPS. Backward compatible, microMIPS is said to combine recoded and new 16- and 32-bit instructions, incorporating all MIPS32 instructions and Application Specific Extensions (ASEs) including MIPS-3D ASE, MIPS DSP ASE, MIPS MT ASE, and SmartMIPS ASE.

Additionally, microMIPS is said to supply new instructions for advanced code-size reduction.

The 1.5 DMIPS/MHz performance figure cited for microMIPS is said to be based on a 180 MHz clock rate using 130 nm fabrication.

With these new developments, Linux developers will now likely focus on the M-14Kc core, which builds on the M-14K platform with additional features that are said to target embedded applications such as home entertainment, home networking and personal mobile entertainment devices.

The core is said to offer a full cache controller and translation look-aside buffer memory management unit.

The M14Kc targets applications that "require a compact footprint but also the ability to execute increasingly complex software algorithms on an RTOS or Linux," says the company.

The M14Kc core is based on the MIPS32 4KEc micro-architecture, which provides a Linux and Java engine that is said to be suitable for Android-driven mobile devices.

Both new cores are supported with software development tools, including the Eclipse-based MIPS Navigator Integrated Component Suite (ICS) and System Navigator probes for debugging. In addition, third party vendors have announced support for the cores.

Support testimonials were offered from Express Logic and Micrium. Specific support for the M14Kc core was announced by Mentor Graphics for its Linux, Android, and Nucleus distributions, as well as by MontaVista Software for MontaVista Linux 6, and Timesys for its LinuxLink development framework.

Additionally, MIPS will provide simulation models for the M-14K and M-14Kc cores, based on Carbon Design Systems technology, for verification in SystemC and co-simulation environments.

Software developers, meanwhile, will be able to call upon fast instruction set simulators, developed in conjunction with Imperas, for use in software development and virtual platforms, says the company.

Art Swift, vice president of marketing at MIPS says "increasing amounts of signal processing and higher speed connectivity are driving up the performance requirements in MCUs and many cost-sensitive embedded applications, while still requiring a very small silicon footprint."

He added "we're enabling our customers to develop high-performance devices in smaller form factors to significantly decrease development costs."

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Source: MIPS Technologies.

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